EP1875683

• Koninklijke Philips Electronics N.V.since Dec 7, 2007

An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103, 104) and a data communication network (100) comprising a plurality of network stations being interconnected via a plurality of communication channels (150) for communicating data packages between the functional blocks (101, 102, 103, 104). Each data package comprising N data elements including a data element comprising routing information for the network stations (110, 120, 130, 140), N being an integer of at least two. The plurality of network stations comprises a plurality of data routers (110, 120, 130, 140) and a plurality of network interfaces, each of the data routers (110, 120, 130, 140) being coupled to a functional block (101, 102, 103, 104) via a network interface (105-108), the data communication network (100) comprising a first network station (140) and a second network station (120) interconnected through a first communication channel (150), the network comprising M*N data storage elements (160), M being a positive integer, for introducing a delay of M*N cycles on the first communication channel (150).An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103, 104) and a plurality of data routers (110, 120, 130, 140), each being coupled to a functional block (101, 102, 103, 104). The introduction of a delay of one or more data packages on a slow communication channel (150) facilitates an increase of the maximum clock speed of the data communication over the data communication network (100).

From the international application WO2006111931