ACT_7940/2024
HIGH SPEED PACKET PROCESSING IN A WIRELESS NETWORK
Lionra Technologies Ltd. sued Cisco Systems GmbH and Cisco Systems Inc. before the Hamburg Local Division for infringement of EP 2 201 740, a patent relating to DMA-based latency reduction in wireless packet processing. The court dismissed the infringement claim after construing the 'simultaneous header writing' requirement against the patent description and finding Cisco's Ingress FIFO architecture did not meet it. The revocation counterclaim was also dismissed, and costs were split 40% (claimant) / 60% (defendants).
Patent claims must be interpreted with reference to description and drawings, not based on literal wording alone
RespondentLegal basis: Art. 69 EPC; Art. 25 UPCANote: Hamburg LD held that claim construction must incorporate express disclosures in the description; the description limited the DMA-based simultaneous header-writing requirement.
Cisco products do not implement simultaneous header writing by a DMA into packet buffer memory and protocol stack layer memory as required by the patent
RespondentLegal basis: Art. 25 UPCANote: The court found that the Ingress FIFO does not simultaneously write headers to both a packet buffer and protocol-stack layer memory; simultaneity criterion was not met.
Cisco products implement the claimed DMA-based simultaneous header-writing mechanism
ClaimantLegal basis: Art. 69 EPC; Art. 25 UPCAReason: The Ingress FIFO sends only the first 256 bytes as a single data stream to the IFC; headers are not immediately available in the stack-layer memory but must first be extracted by a parser — the simultaneity criterion is absent.
Auxiliary requests establish infringement on alternative claim readings
ClaimantReason: Because the main claim features were not implemented, the auxiliary requests were not separately evaluated.
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The patent claims a DMA that simultaneously writes the header into a packet buffer store and into the memory in the respective layer of the protocol stack (as illustrated in Figure 4). The court construed 'simultaneously' strictly: the Cisco Ingress FIFO writes only 256 bytes as a single stream; the header is not immediately available in the stack-layer memory but requires extraction by a parser. Neither the Ingress FIFO alone nor the combination of Ingress FIFO and IFC satisfy the simultaneity requirement.