UPC CFI 64/2024

Width converters and rate adapters used in the accused NoC architecture do not delay whole data packages by M*N clock cycles as required by feature group 4 of claim 1 (and correspondingly claim 8); each data element is delayed by a different number of clock cycles, and data packages of varying size have no fixed correspondence to a fixed number of M*N data storage elements.

The patent-in-suit is not inadmissibly extended: the requirement that a complete data package is transmitted within N clock cycles is implicit in (a clear and unambiguous consequence of) the application as filed, so the amendment of claims 1 and 8 during examination is not an impermissible intermediate generalisation.

The claimed subject matter is novel over “Bertozzi” and involves an inventive step, because “Bertozzi” is not a suitable/realistic starting point in the prior art and does not point the skilled person toward the claimed solution.

The Arteris NoC Chapter, together with Qualcomm's acquisition of Arteris technology and personnel, plausibly evidences that the accused NoC ICs use M*N data storage elements to delay whole data packages, warranting an order to produce Qualcomm's source code and technical documents.

In the alternative, the Qualcomm NoC ICs infringe feature group 4 by equivalence.

The amendment of claims 1 and 8 during examination constitutes an inadmissible intermediate generalisation of the application as filed, and the claims lack novelty over “Bertozzi” and lack an inventive step.