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UPC CFI 64/2024

1. März 2024·EP1875683 · INTEGRATED CIRCUIT WITH DATA COMMUNICATION NETWORK AND IC DESIGN METHOD

Verfahrensdetails
Status
Case Closed (Keine Verletzung)
Verfahrensart
Verletzung
Kategorie
Hauptverletzungsklage
Parteien
Kläger
Vertreter
Division
Munich LD
Technologie
  • Electrical engineering
    Digital communication
Sprache
English
Erste Entscheidung
11. März 2026
Im Vergleich
Die Bilanz des Gerichts für diese Art von Verfahren, gezählt in erstinstanzlichen Entscheidungen. Eine Zahl in Klammern gibt an, auf wie vielen Entscheidungen eine Quote beruht.
Verletzung festgestelltMedian Tage bis zur ersten Entscheidung
Gesamt-UPC53% (62/117)124
Munich LDGesperrtGesperrt
Richter Daniel VossGesperrtGesperrt
Richter Pierluigi PerrottiGesperrtGesperrt
Richter Georg WernerGesperrtGesperrt
Richter Andrea ScillettaGesperrtGesperrt

Vor dem UPC: Network System Technologies LLC (77 Verfahren)·Samsung Group (57 Verfahren)

Dieser Streit umfasst 10 weitere Verfahren

UPC CoA 68/2026·UPC CoA 69/2026·UPC CoA 70/2026·UPC CoA 71/2026·UPC CoA 72/2026 und 5 weitere

9 weitere Beklagte zum selben oder einem verwandten Patent

UPC CoA 217/2024·UPC CoA 218/2024·UPC CoA 224/2024·CC 24453/2024·UPC CFI 167/2024 und 4 weitere

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Weitere Verfahren: Munich LD·2024

Entscheidungen
  • 2026-03-11
    Infringement ActionÖffentlich

    Zusammenfassung: The Munich Local Division (Panel 2) dismissed Network System Technologies' infringement action against Qualcomm's NoC-based chips under EP 1875683, finding that the Arteris-derived width converters and rate adapters relied on do not delay whole data packages by M*N clock cycles as required by claims 1 and 8, and rejecting infringement by equivalence and the request to order production of Qualcomm's source code under R.190 RoP. On the linked counterclaim for revocation (UPC_CFI_450/2024), the Court rejected Qualcomm's added-matter, novelty (over “Bertozzi”) and inventive-step attacks and held the patent valid as granted.

    Rechtsfragen anzeigen (7)
    • Claim construction of ‘M*N data storage elements’ introducing a delay of M*N clock cycles on the first communication channel (feature group 4)
    • Non-infringement: width converters and rate adapters do not delay whole data packages by M*N clock cycles
    • Infringement by equivalence rejected for failure to identify a specific substitute means, its function and technical effect
    • Request to produce evidence (source code) under Art. 59(1) UPCA / R.190 RoP rejected as an impermissible ‘fishing expedition’
    • Added matter / inadmissible extension (intermediate generalisation), Art. 65(2) UPCA, Art. 138(1)(c) EPC, Art. 123(2) EPC
    • Novelty over “Bertozzi” (“Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip”), Art. 54 EPC
    • Inventive step, Art. 56 EPC
DokumenttitelDatumÖffentlich
Anordnung2026-04-14Nicht öffentlich
Order2026-04-14Öffentlich
Receipt2026-04-13Nicht öffentlich
Cover sheet2026-04-13Nicht öffentlich
Application document Applicant2026-04-13Nicht öffentlich
Hearing recording reference document2026-04-01Nicht öffentlich
Decision2026-03-16Öffentlich
Verfahren abgeschlossen2026-03-11Nicht öffentlich
Entscheidung2026-03-11Nicht öffentlich
Decision2026-03-11Nicht öffentlich
Angenommene Argumente
Was das Gericht akzeptiert hat — nach Partei.
  • Width converters and rate adapters used in the accused NoC architecture do not delay whole data packages by M*N clock cycles as required by feature group 4 of claim 1 (and correspondingly claim 8); each data element is delayed by a different number of clock cycles, and data packages of varying size have no fixed correspondence to a fixed number of M*N data storage elements.

    BeklagterRechtsgrundlage: Non-infringement – claim construction of feature group 4 of claim 1 / claim 8
  • The patent-in-suit is not inadmissibly extended: the requirement that a complete data package is transmitted within N clock cycles is implicit in (a clear and unambiguous consequence of) the application as filed, so the amendment of claims 1 and 8 during examination is not an impermissible intermediate generalisation.

    KlägerRechtsgrundlage: Art. 65(2) UPCA in conjunction with Art. 138(1)(c) EPC / Art. 123(2) EPC (added matter)
  • The claimed subject matter is novel over “Bertozzi” and involves an inventive step, because “Bertozzi” is not a suitable/realistic starting point in the prior art and does not point the skilled person toward the claimed solution.

    KlägerRechtsgrundlage: Art. 54 EPC (novelty), Art. 56 EPC (inventive step)
Zurückgewiesene Argumente
Was das Gericht nicht akzeptiert hat — und warum.
  • The Arteris NoC Chapter, together with Qualcomm's acquisition of Arteris technology and personnel, plausibly evidences that the accused NoC ICs use M*N data storage elements to delay whole data packages, warranting an order to produce Qualcomm's source code and technical documents.

    KlägerRechtsgrundlage: Art. 59(1) UPCA, R.190.1 RoP – rejected for lack of plausible evidence in support of the claim and as amounting to a US-style ‘fishing expedition’
  • In the alternative, the Qualcomm NoC ICs infringe feature group 4 by equivalence.

    KlägerRechtsgrundlage: Doctrine of equivalence – rejected because the Claimant did not specifically explain which feature is realised by which substitute means, its function and its technical effect
  • The amendment of claims 1 and 8 during examination constitutes an inadmissible intermediate generalisation of the application as filed, and the claims lack novelty over “Bertozzi” and lack an inventive step.

    BeklagterRechtsgrundlage: Art. 138(1)(c) EPC / Art. 123(2) EPC (added matter); Art. 54 EPC (novelty); Art. 56 EPC (inventive step) – all rejected, patent maintained as granted