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UPC CFI 64/2024

Mar 1, 2024·EP1875683 · INTEGRATED CIRCUIT WITH DATA COMMUNICATION NETWORK AND IC DESIGN METHOD

Case details
Status
Case Closed (No infringement)
Action
Infringement
Category
Main infringement action
Parties
Claimants
Representatives
Respondents
Representatives
Division
Munich LD
Technology
  • Electrical engineering
    Digital communication
Language
English
First decided
Mar 11, 2026
How this compares
The court's record for this kind of case, counted in first-instance rulings. A figure in brackets is the number of rulings a rate rests on.
Infringement foundMedian days to first decision
All UPC53% (62/117)124
Munich LDLockedLocked
Judge Daniel VossLockedLocked
Judge Pierluigi PerrottiLockedLocked
Judge Georg WernerLockedLocked
Judge Andrea ScillettaLockedLocked

At the UPC: Network System Technologies LLC (77 cases)·Samsung Group (57 cases)

This dispute contains 10 other proceedings

UPC CoA 68/2026·UPC CoA 69/2026·UPC CoA 70/2026·UPC CoA 71/2026·UPC CoA 72/2026 and 5 more

9 other defendants litigating the same or a related patent

UPC CoA 217/2024·UPC CoA 218/2024·UPC CoA 224/2024·CC 24453/2024·UPC CFI 167/2024 and 4 more

Start a free trial to see how each one ended.

More cases: Munich LD·2024

Decisions
  • 2026-03-11
    Infringement ActionPublic

    Summary: The Munich Local Division (Panel 2) dismissed Network System Technologies' infringement action against Qualcomm's NoC-based chips under EP 1875683, finding that the Arteris-derived width converters and rate adapters relied on do not delay whole data packages by M*N clock cycles as required by claims 1 and 8, and rejecting infringement by equivalence and the request to order production of Qualcomm's source code under R.190 RoP. On the linked counterclaim for revocation (UPC_CFI_450/2024), the Court rejected Qualcomm's added-matter, novelty (over “Bertozzi”) and inventive-step attacks and held the patent valid as granted.

    Show the legal issues (7)
    • Claim construction of ‘M*N data storage elements’ introducing a delay of M*N clock cycles on the first communication channel (feature group 4)
    • Non-infringement: width converters and rate adapters do not delay whole data packages by M*N clock cycles
    • Infringement by equivalence rejected for failure to identify a specific substitute means, its function and technical effect
    • Request to produce evidence (source code) under Art. 59(1) UPCA / R.190 RoP rejected as an impermissible ‘fishing expedition’
    • Added matter / inadmissible extension (intermediate generalisation), Art. 65(2) UPCA, Art. 138(1)(c) EPC, Art. 123(2) EPC
    • Novelty over “Bertozzi” (“Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip”), Art. 54 EPC
    • Inventive step, Art. 56 EPC
Document titleDatePublic
Order2026-04-14Not public
Order2026-04-14Public
Receipt2026-04-13Not public
Cover sheet2026-04-13Not public
Application document Applicant2026-04-13Not public
Hearing recording reference document2026-04-01Not public
Decision2026-03-16Public
Case closed2026-03-11Not public
Decision2026-03-11Not public
Decision2026-03-11Not public
Accepted arguments
What the court agreed with — by party.
  • Width converters and rate adapters used in the accused NoC architecture do not delay whole data packages by M*N clock cycles as required by feature group 4 of claim 1 (and correspondingly claim 8); each data element is delayed by a different number of clock cycles, and data packages of varying size have no fixed correspondence to a fixed number of M*N data storage elements.

    RespondentLegal basis: Non-infringement – claim construction of feature group 4 of claim 1 / claim 8
  • The patent-in-suit is not inadmissibly extended: the requirement that a complete data package is transmitted within N clock cycles is implicit in (a clear and unambiguous consequence of) the application as filed, so the amendment of claims 1 and 8 during examination is not an impermissible intermediate generalisation.

    ClaimantLegal basis: Art. 65(2) UPCA in conjunction with Art. 138(1)(c) EPC / Art. 123(2) EPC (added matter)
  • The claimed subject matter is novel over “Bertozzi” and involves an inventive step, because “Bertozzi” is not a suitable/realistic starting point in the prior art and does not point the skilled person toward the claimed solution.

    ClaimantLegal basis: Art. 54 EPC (novelty), Art. 56 EPC (inventive step)
Rejected arguments
What the court did not agree with — and why.
  • The Arteris NoC Chapter, together with Qualcomm's acquisition of Arteris technology and personnel, plausibly evidences that the accused NoC ICs use M*N data storage elements to delay whole data packages, warranting an order to produce Qualcomm's source code and technical documents.

    ClaimantLegal basis: Art. 59(1) UPCA, R.190.1 RoP – rejected for lack of plausible evidence in support of the claim and as amounting to a US-style ‘fishing expedition’
  • In the alternative, the Qualcomm NoC ICs infringe feature group 4 by equivalence.

    ClaimantLegal basis: Doctrine of equivalence – rejected because the Claimant did not specifically explain which feature is realised by which substitute means, its function and its technical effect
  • The amendment of claims 1 and 8 during examination constitutes an inadmissible intermediate generalisation of the application as filed, and the claims lack novelty over “Bertozzi” and lack an inventive step.

    RespondentLegal basis: Art. 138(1)(c) EPC / Art. 123(2) EPC (added matter); Art. 54 EPC (novelty); Art. 56 EPC (inventive step) – all rejected, patent maintained as granted